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This version: Mar. 1999
Semiconductor MSC23CV43257D-xxBS8
4,194,304-word x 32-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSC23CV43257D-xxBS8 is a fully decoded, 4,194,304-word x 32-bit CMOS dynamic random access memory module composed of eight 16Mb DRAMs (4Mx4) in TSOP packages mounted with eight decoupling capacitors on a 72-pin glass epoxy small outline package. This module supports any application where high density and large capacity of storage memory are required.
FEATURES
* 4,194,304-word x 32-bit organization * 72-pin Small Outline Dual In-line Memory module MSC23CV43257D-xxBS8 : Gold tab * Single +3.3V supply 0.3V tolerance * Input : LVTTL compatible * Output : LVTTL compatible, 3-state * Refresh : 2048cycles/32ms * /CAS before /RAS refresh, hidden refresh, /RAS only refresh capability * Fast page mode with EDO capability * Multi-bit test mode capability * 11/11 Addressing (Row/Column)
PRODUCT FAMILY
Access Time (Max.) Family tRAC MSC23CV43257D-60BS8 MSC23CV43257D-70BS8 60ns 70ns tAA 30ns 35ns tCAC 15ns 20ns Cycle Time (Min.) 104ns 124ns Power Dissipation
Operating (Max.) Standby (Max.)
2592mW 14.4mW 2304mW
Semiconductor
MSC23CV43257D
MODULE OUTLINE
MSC23CV43257D-xxBS8
(Unit : mm) 3.80Max.
25.40.13
3.180.13 2.00.13
1 2.62Typ. *1
71
5.5Min.
44.450.1 59.690.2
1.000.1
*1 The common size difference of the board width 19.78mm of its height is specified as 0.2. The value above 19.78mm is specified as 0.5.
R2.0 1.00.1
17.780.13
0.25 Max.
1.80.1 2-1.8 3.03
72
2 3.25Typ. 44.450.1 51.660.1 5.00 R2.0 0.23 Min. 1.270.1
Semiconductor
MSC23CV43257D
PIN CONFIGURATION
Front Side Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 Pin Name VSS DQ1 DQ3 DQ5 DQ7 PD1 A1 A3 A5 A10 DQ8 DQ10 DQ12 DQ14 NC A8 NC DQ15 Pin No. 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 Pin Name DQ16 VSS /CAS2 /CAS1 NC /WE DQ18 DQ20 DQ22 NC DQ25 DQ27 VCC DQ30 NC PD3 PD5 PD7 Pin No. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 Back Side Pin Name DQ0 DQ2 DQ4 DQ6 VCC A0 A2 A4 A6 NC DQ9 DQ11 DQ13 A7 VCC A9 /RAS2 NC Pin No. 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 Pin Name DQ17 /CAS0 /CAS3 /RAS0 NC NC DQ19 DQ21 DQ23 DQ24 DQ26 DQ28 DQ29 DQ31 PD2 PD4 PD6 VSS
Presence Detect Pins
Pin No. 11 66 67 68 69 70 71 Pin Name PD1 PD2 PD3 PD4 PD5 PD6 PD7 -60 NC NC VSS NC NC NC NC -70 NC NC VSS NC VSS NC NC
Semiconductor
MSC23CV43257D
BLOCK DIAGRAM
A0-A10 /RAS0 /CAS0 /WE A0-A10 /RAS /CAS /WE VCC A0-A10 /RAS /CAS /WE VCC DQ DQ DQ DQ /OE VSS DQ DQ DQ DQ /OE VSS DQ0 DQ1 DQ2 DQ3
/RAS2 /CAS2
A0-A10 /RAS /CAS /WE VCC
DQ DQ DQ DQ /OE VSS DQ DQ DQ DQ /OE VSS
DQ16 DQ17 DQ18 DQ19
DQ4 DQ5 DQ6 DQ7
A0-A10 /RAS /CAS /WE VCC
DQ20 DQ21 DQ22 DQ23
A0-A10 /RAS /CAS /WE VCC
DQ DQ DQ DQ /OE VSS
DQ8 DQ9 DQ10 DQ11
A0-A10 /RAS /CAS /WE VCC
DQ DQ DQ DQ /OE VSS
DQ24 DQ25 DQ26 DQ27
A0-A10 /RAS /CAS /WE VCC /CAS1 VCC VSS C1-C8
DQ DQ DQ DQ /OE VSS
DQ12 DQ13 DQ14 DQ15
A0-A10 /RAS /CAS /WE VCC /CAS3
DQ DQ DQ DQ /OE VSS
DQ28 DQ29 DQ30 DQ31
Semiconductor
MSC23CV43257D
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VIN, VOUT VCC IOS PD * TOPR TSTG * Ta = 25C Rating -0.5 to +4.6 -0.5 to +4.6 50 8 0 to +70 -40 to +125 Unit V V mA W C C
Recommended Operating Conditions
( Ta = 0C to +70C ) Parameter Power Supply Voltage VSS Input High Voltage Input Low Voltage VIH VIL 0 2.0 -0.3 0 0 VCC+0.3 0.8 V V V Symbol VCC Min. 3.0 Typ. 3.3 Max. 3.6 Unit V
Capacitance
( VCC = 3.3V 0.3V, Ta = 25C, f = 1 MHz ) Parameter Input Capacitance (A0 - A10) Input Capacitance (/WE) Input Capacitance (/RAS0, /RAS2) Input Capacitance (/CAS0- /CAS3) I/O Capacitance (DQ0 - DQ31) Symbol CIN1 CIN2 CIN3 CIN4 CDQ Typ. Max. 57 65 35 20 16 Unit pF pF pF pF pF
Semiconductor
MSC23CV43257D
DC Characteristics
(VCC = 3.3V 0.3V, Ta = 0C to +70C ) -60 Parameter Symbol Condition Min. Input Leakage Current ILI 0V VIN VCC+0.3V; All other pins not under test = 0V DQ disable 0V VOUT VCC IOH = -2.0mA IOL = 2.0mA /RAS, /CAS cycling, tRC = Min. /RAS, /CAS = VIH Power supply current (Standby) Average Power Supply Current (/RAS only refresh) Average Power Supply Current (/CAS before /RAS refresh) Average Power Supply Current (Fast Page Mode) ICC2 /RAS, /CAS VCC -0.2V /RAS cycling, /CAS = VIH, tRC = Min. /RAS cycling, /CAS before /RAS /RAS = VIL, /CAS cycling, tHPC = Min. -80 Max. 80 Min. -80 Max. 80 A -70 Unit Note
Output Leakage Current Output High Voltage Output Low Voltage Average Power Supply Current (Operating)
ILO VOH VOL ICC1
-10 2.4 0 -
10 VCC 0.4 720 16 4
-10 2.4 0 -
10 VCC 0.4 640 16 4
A V V mA mA mA 1, 2 1 1
ICC3
-
720
-
640
mA
1, 2
ICC6
-
720
-
640
mA
1, 2
ICC7
-
720
-
640
mA
1, 3
Notes: 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while /RAS = VIL. 3. The address can be changed once or less while /CAS = VIH.
Semiconductor
MSC23CV43257D
AC Characteristics (1/2)
(VCC = 3.3V 0.3V, Ta = 0C to +70C ) Note: 1, 2, 3, 10, 11 -60 Parameter Symbol Min. Random Read or Write Cycle Time Fast Page Mode Cycle Time Access Time from /RAS Access Time from /CAS Access Time from Column Address Access Time from /CAS Precharge Output Low Impedance Time from /CAS Data Output Hold After /CAS Low /CAS to Data Output Buffer Turn-off Delay Time /RAS to Data Output Buffer Turn-off Delay Time /WE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period /RAS Precharge Time /RAS Pulse Width /RAS Pulse Width (Fast Page Mode with EDO) /RAS Hold Time /CAS Precharge Time (Fast Page Mode with EDO) /CAS Pulse Width /CAS Hold Time /CAS to /RAS Precharge Time /RAS Hold Time from /CAS Precharge /RAS to /CAS Delay Time /RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address to /RAS Lead Time Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to /RAS tRC tHPC tRAC tCAC tAA t CPA tCLZ tDOH tCEZ tREZ tWEZ tT tREF tRP tRAS tRASP tRSH tCP tCAS tCSH tCRP tRHCP tRCD tRAD tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH 104 25 0 5 0 0 0 1 40 60 60 10 10 10 40 5 35 14 12 0 10 0 10 30 0 0 0 Max. 60 15 30 35 15 15 15 50 32 10K 100K 10K 45 30 Min. 124 30 0 5 0 0 0 1 50 70 70 13 10 13 45 5 40 14 12 0 10 0 13 35 0 0 0 Max. 70 20 35 40 20 20 20 50 32 10K 100K 10K 50 35 ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 9 5 6 7,8 7,8 7 3 4, 5, 6 4, 5 4, 6 4 4 -70 Unit Note
Semiconductor
MSC23CV43257D
AC Characteristics (2/2)
(VCC = 3.3V 0.3V, Ta = 0C to +70C ) Note: 1, 2, 3, 10, 11 -60 Parameter Symbol Min. Write Command Set-up Time Write Command Hold Time Write Command Pulse Width /WE Pulse Width (DQ Disable) Write Command to /RAS Lead Time Write Command to /CAS Lead Time Data-in Set-up Time Data-in Hold Time /CAS Active Delay Time from /RAS Precharge /RAS to /CAS Set-up Time (/CAS before /RAS) /RAS to /CAS Hold Time (/CAS before /RAS) /WE to /RAS Precharge Time (/CAS before /RAS) /WE Hold Time from /RAS (/CAS before /RAS) /RAS to /WE Set-up Time (Test Mode) /RAS to /WE Hold Time (Test Mode) tWCS tWCH tWP tWPE tRWL tCWL tDS tDH tRPC tCSR tCHR tWRP tWRH tWTS tWTH 0 10 10 10 10 10 0 10 5 5 10 10 10 10 10 Max. Min. 0 13 10 10 13 13 0 13 5 5 10 10 10 10 10 Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -70 Unit Note
Semiconductor
MSC23CV43257D
Notes: 1. A start-up delay of 200s is required after power-up, followed by a minimum of eight initialization cycles (/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved. 2. The AC characteristics assumes tT = 2ns. 3. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition time (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1TTL loads and 100pF. The output timing reference levels are VOH = 2.0V and VOL = 0.8V. 5. Operation within the tRCD(Max.) limit ensures that tRAC(Max.) can be met. tRCD(Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD(Max.) limit ensures that tRAC(Max.) can be met. tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then the access time is controlled by tAA. 7. tCEZ(Max.), tREZ(Max.) and tWEZ(Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ or tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is an 8-bit parallel test function. In a test mode CA0, CA1 and CA10 are not used. In a read cycle, if 8 data bits are equal, the DQ pin will indicate a high level. If the 8 data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a /RAS only refresh cycle or a /CAS before /RAS refresh cycle. 11. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet.

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